ada4806493
新增功能： - waveformTracer.ts: 调用 waveform_trace.exe 的工具实现 - toolExecutor.ts: 添加 waveform_trace 工具分发 - types/api.ts: 添加 WaveformTraceArgs 类型定义 工具源码 (tools/waveform_trace/src/): - AST 解析 + BFS 信号追踪 - VCD 波形解析 - 修复通用 testbench 支持 配置文件： - .gitignore: 排除 exe 和打包产物 - .vscodeignore: 发布时排除源码 - build.bat/build.sh: 打包脚本
71 lines
2.9 KiB
Python
71 lines
2.9 KiB
Python
#
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# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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# Author : Chia-Tung (Mark) Ho, NVIDIA
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#
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import copy
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import re
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from collections import deque
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from graph_builder import generate_top_logic_graph
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# use class
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class DebugGraph:
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def __init__(self, verilog_filelist: list[str]):
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self.filelist = verilog_filelist
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self.graph = generate_top_logic_graph(verilog_filelist)
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# print(list(self.graph.nodes(data=True)))
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def get_k_control_signals(self, target_signals: list[str], k:int, signal_only: bool=False) -> list[str]:
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control_signals = {}
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signal_level_tracer = []
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# queue
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q = deque()
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tmp_q = deque()
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for signal in target_signals:
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# store (predecessors, controlled signal)
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q.append((signal, signal))
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control_signals[signal] = self.graph.nodes[signal]['lines']
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# BFS
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for l in range (k + 1):
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# traverse l layers
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tmp_q.clear()
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level_signal_control_rels = []
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while len(q) > 0:
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cur_signal = q.popleft()
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level_signal_control_rels.append(cur_signal[0] + "->" + cur_signal[1])
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if cur_signal[0] not in control_signals:
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if self.graph.has_edge(cur_signal[0], cur_signal[1]):
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# must be the control signals through the edge
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control_signals[cur_signal[0]] = self.graph[cur_signal[0]][cur_signal[1]]['lines']
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else:
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print("[Error] Edge not found! - ", cur_signal)
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# find the predecessors
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controls = self.graph.predecessors(cur_signal[0])
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for c in controls:
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if c in control_signals:
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continue
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# exclude the parameter
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if 'type' in self.graph.nodes[c] and self.graph.nodes[c]['type'] in ["Parameter", "Localparam"]:
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continue
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if signal_only and (re.match('^Always', c) or re.match('^Assign', c) or re.match('^Module', c) or re.match('^IntConst', c)):
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continue
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# store (predecessors, controlled signal)
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tmp_q.append((c, cur_signal[0]))
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# swap the q
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assert(len(q) == 0)
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print(tmp_q)
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q = copy.deepcopy(tmp_q)
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# record the signal relations
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signal_level_tracer.append(level_signal_control_rels)
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return control_signals, signal_level_tracer
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if __name__ == '__main__':
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debug_graph_tracer = DebugGraph(["/home/scratch.chiatungh_nvresearch/hardware-agent-marco/hardware_agent/examples/verilog_testcases/fsm_serialdata.v"])
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print(debug_graph_tracer.get_k_control_signals(['out_byte', 'done'], k=3, signal_only=True))
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