401 lines
10 KiB
TypeScript
401 lines
10 KiB
TypeScript
import * as vscode from "vscode";
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import * as fs from "fs";
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import * as path from "path";
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import { spawn } from "child_process";
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import { promisify } from "util";
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// 使用 spawn 来执行命令，正确处理路径空格
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function execCommand(
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command: string,
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args: string[],
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options: { cwd: string; env?: any }
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): Promise<{ stdout: string; stderr: string }> {
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return new Promise((resolve, reject) => {
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// 在 Windows 上，如果路径包含空格，不使用 shell，直接用 spawn
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// spawn 在不使用 shell 时会正确处理带空格的路径
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const child = spawn(command, args, {
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cwd: options.cwd,
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env: options.env || process.env,
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windowsHide: true,
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shell: false, // 不使用 shell，让 spawn 直接执行
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});
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let stdout = "";
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let stderr = "";
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// 在 Windows 上使用 GBK 编码解码输出
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const encoding = process.platform === 'win32' ? 'gbk' : 'utf8';
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child.stdout.on("data", (data) => {
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try {
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// 尝试使用 iconv-lite 解码（如果可用）
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const iconv = require('iconv-lite');
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stdout += iconv.decode(data, encoding);
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} catch {
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// 如果 iconv-lite 不可用，使用默认解码
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stdout += data.toString('utf8');
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}
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});
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child.stderr.on("data", (data) => {
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try {
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const iconv = require('iconv-lite');
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stderr += iconv.decode(data, encoding);
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} catch {
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stderr += data.toString('utf8');
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}
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});
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child.on("close", (code) => {
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if (code === 0) {
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resolve({ stdout, stderr });
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} else {
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const error: any = new Error(`Command failed with exit code ${code}`);
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error.stdout = stdout;
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error.stderr = stderr;
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error.code = code;
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reject(error);
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}
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});
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child.on("error", (error) => {
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reject(error);
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});
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});
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}
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/**
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* Verilog 项目文件检查结果
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*/
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export interface VerilogProjectCheck {
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isComplete: boolean;
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hasTopModule: boolean;
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hasTestbench: boolean;
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topModuleFile?: string;
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testbenchFile?: string;
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allVerilogFiles: string[];
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missingFiles: string[];
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errors: string[];
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}
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/**
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* VCD 生成结果
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*/
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export interface VCDGenerationResult {
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success: boolean;
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vcdFilePath?: string;
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outputPath?: string;
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message: string;
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stdout?: string;
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stderr?: string;
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}
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/**
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* 检查项目中的 Verilog 文件完整性
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*/
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export async function checkVerilogProject(
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projectPath: string
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): Promise<VerilogProjectCheck> {
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const result: VerilogProjectCheck = {
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isComplete: false,
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hasTopModule: false,
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hasTestbench: false,
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allVerilogFiles: [],
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missingFiles: [],
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errors: [],
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};
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try {
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// 检查项目路径是否存在
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if (!fs.existsSync(projectPath)) {
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result.errors.push(`项目路径不存在: ${projectPath}`);
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return result;
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}
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// 查找所有 Verilog 文件 (.v, .sv)
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const verilogFiles = findVerilogFiles(projectPath);
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result.allVerilogFiles = verilogFiles;
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if (verilogFiles.length === 0) {
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result.errors.push("项目中没有找到 Verilog 文件 (.v 或 .sv)");
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return result;
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}
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// 分析文件内容，查找 top module 和 testbench
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for (const file of verilogFiles) {
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const content = fs.readFileSync(file, "utf-8");
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const fileName = path.basename(file).toLowerCase();
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// 检查是否是 testbench 文件
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if (
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fileName.includes("tb") ||
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fileName.includes("test") ||
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content.includes("$dumpfile") ||
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content.includes("$dumpvars")
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) {
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result.hasTestbench = true;
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result.testbenchFile = file;
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}
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// 检查是否包含 module 定义（可能是 top module）
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if (content.match(/module\s+\w+/)) {
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if (!result.hasTopModule && !fileName.includes("tb")) {
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result.hasTopModule = true;
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result.topModuleFile = file;
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}
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}
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}
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// 检查完整性
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if (!result.hasTopModule) {
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result.missingFiles.push("缺少顶层模块文件");
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}
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if (!result.hasTestbench) {
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result.missingFiles.push("缺少 testbench 文件");
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}
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result.isComplete = result.hasTopModule && result.hasTestbench;
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return result;
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} catch (error) {
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result.errors.push(
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`检查项目时出错: ${error instanceof Error ? error.message : "未知错误"}`
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);
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return result;
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}
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}
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/**
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* 递归查找目录下所有 Verilog 文件
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*/
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function findVerilogFiles(dir: string): string[] {
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const verilogFiles: string[] = [];
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function searchDir(currentDir: string) {
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const files = fs.readdirSync(currentDir);
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for (const file of files) {
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const filePath = path.join(currentDir, file);
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const stat = fs.statSync(filePath);
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if (stat.isDirectory()) {
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// 跳过 node_modules 等目录
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if (!file.startsWith(".") && file !== "node_modules") {
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searchDir(filePath);
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}
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} else if (stat.isFile()) {
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const ext = path.extname(file).toLowerCase();
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if (ext === ".v" || ext === ".sv") {
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verilogFiles.push(filePath);
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}
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}
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}
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}
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searchDir(dir);
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return verilogFiles;
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}
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/**
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* 获取 iverilog 可执行文件路径
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*/
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function getIverilogPath(extensionPath: string): string {
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const platform = process.platform;
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let iverilogBin = "";
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if (platform === "win32") {
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iverilogBin = path.join(extensionPath, "tools", "iverilog", "bin", "iverilog.exe");
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} else if (platform === "darwin") {
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iverilogBin = path.join(extensionPath, "tools", "iverilog", "bin", "iverilog");
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} else {
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// Linux
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iverilogBin = path.join(extensionPath, "tools", "iverilog", "bin", "iverilog");
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}
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// 如果插件包中没有，尝试使用系统安装的 iverilog
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if (!fs.existsSync(iverilogBin)) {
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return "iverilog"; // 使用系统 PATH 中的 iverilog
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}
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return iverilogBin;
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}
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/**
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* 获取 vvp 可执行文件路径
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*/
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function getVvpPath(extensionPath: string): string {
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const platform = process.platform;
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let vvpBin = "";
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if (platform === "win32") {
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vvpBin = path.join(extensionPath, "tools", "iverilog", "bin", "vvp.exe");
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} else if (platform === "darwin") {
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vvpBin = path.join(extensionPath, "tools", "iverilog", "bin", "vvp");
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} else {
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// Linux
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vvpBin = path.join(extensionPath, "tools", "iverilog", "bin", "vvp");
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}
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// 如果插件包中没有，尝试使用系统安装的 vvp
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if (!fs.existsSync(vvpBin)) {
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return "vvp"; // 使用系统 PATH 中的 vvp
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}
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return vvpBin;
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}
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/**
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* 运行 iverilog 生成 VCD 文件
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*/
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export async function generateVCD(
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projectPath: string,
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extensionPath: string
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): Promise<VCDGenerationResult> {
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try {
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// 1. 检查项目完整性
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const projectCheck = await checkVerilogProject(projectPath);
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if (!projectCheck.isComplete) {
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return {
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success: false,
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message: `项目文件不完整:\n${projectCheck.missingFiles.join("\n")}\n${projectCheck.errors.join("\n")}`,
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};
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}
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// 2. 获取 iverilog 和 vvp 路径
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const iverilogPath = getIverilogPath(extensionPath);
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const vvpPath = getVvpPath(extensionPath);
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// 3. 准备输出路径
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const outputDir = projectPath;
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const outputFile = path.join(outputDir, "simulation.vvp");
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// 4. 设置环境变量，确保 iverilog 能找到库文件
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const libPath = path.join(extensionPath, "tools", "iverilog", "lib");
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const env = {
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...process.env,
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IVERILOG_ROOT: path.join(extensionPath, "tools", "iverilog"),
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};
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// 5. 构建 iverilog 编译参数
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const compileArgs = ["-o", outputFile, ...projectCheck.allVerilogFiles];
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console.log("执行编译命令:", iverilogPath, compileArgs.join(" "));
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console.log("IVERILOG_ROOT:", env.IVERILOG_ROOT);
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// 6. 执行编译
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let compileResult;
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try {
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compileResult = await execCommand(iverilogPath, compileArgs, {
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cwd: projectPath,
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env: env,
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});
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} catch (error: any) {
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return {
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success: false,
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message: `iverilog 编译失败:\n${error.message}`,
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stderr: error.stderr,
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stdout: error.stdout,
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};
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}
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// 7. 执行仿真生成 VCD
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const simArgs = [outputFile];
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console.log("执行仿真命令:", vvpPath, simArgs.join(" "));
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let simResult;
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try {
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simResult = await execCommand(vvpPath, simArgs, {
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cwd: projectPath,
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env: env,
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});
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} catch (error: any) {
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return {
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success: false,
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message: `VVP 仿真失败:\n${error.message}`,
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stderr: error.stderr,
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stdout: error.stdout,
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};
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}
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// 8. 查找生成的 VCD 文件
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const vcdFiles = fs.readdirSync(projectPath).filter(file => file.endsWith('.vcd'));
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if (vcdFiles.length === 0) {
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return {
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success: false,
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message: "VCD 文件未生成。请确保 testbench 中包含 $dumpfile 和 $dumpvars 语句。",
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stdout: simResult.stdout,
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};
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}
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// 使用找到的第一个 VCD 文件
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const vcdFile = path.join(projectPath, vcdFiles[0]);
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// 9. 清理中间文件
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try {
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if (fs.existsSync(outputFile)) {
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fs.unlinkSync(outputFile);
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}
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} catch (error) {
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// 忽略清理错误
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}
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return {
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success: true,
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vcdFilePath: vcdFile,
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outputPath: projectPath,
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message: `VCD 文件生成成功！\n路径: ${vcdFile}`,
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stdout: simResult.stdout,
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};
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} catch (error) {
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return {
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success: false,
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message: `生成 VCD 文件时出错: ${error instanceof Error ? error.message : "未知错误"}`,
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};
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}
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}
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/**
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* 检查 iverilog 是否可用
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*/
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export async function checkIverilogAvailable(
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extensionPath: string
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): Promise<{ available: boolean; version?: string; message: string }> {
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try {
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const iverilogPath = getIverilogPath(extensionPath);
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// 检查文件是否存在
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if (!fs.existsSync(iverilogPath)) {
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return {
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available: false,
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message: `iverilog 不可用。未找到文件: ${iverilogPath}`,
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};
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}
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// 设置环境变量
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const env = {
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...process.env,
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IVERILOG_ROOT: path.join(extensionPath, "tools", "iverilog"),
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};
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const result = await execCommand(iverilogPath, ["-V"], {
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cwd: path.dirname(iverilogPath),
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env: env,
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});
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const version = result.stdout.trim().split("\n")[0];
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return {
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available: true,
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version: version,
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message: `iverilog 可用: ${version}`,
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};
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} catch (error: any) {
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return {
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available: false,
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message: `iverilog 执行失败: ${error.message}\n${error.stderr || ""}`,
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};
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}
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}
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