18 lines
328 B
Verilog
18 lines
328 B
Verilog
// counter.v - 简单的 4 位计数器模块
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module counter (
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input wire clk,
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input wire rst_n,
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output reg [3:0] count
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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count <= 4'b0000;
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end else begin
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count <= count + 1;
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end
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end
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endmodule
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