feat: 集成 waveform_trace 波形调试工具
新增功能： - waveformTracer.ts: 调用 waveform_trace.exe 的工具实现 - toolExecutor.ts: 添加 waveform_trace 工具分发 - types/api.ts: 添加 WaveformTraceArgs 类型定义 工具源码 (tools/waveform_trace/src/): - AST 解析 + BFS 信号追踪 - VCD 波形解析 - 修复通用 testbench 支持 配置文件： - .gitignore: 排除 exe 和打包产物 - .vscodeignore: 发布时排除源码 - build.bat/build.sh: 打包脚本
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XiaoFeng
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tools/waveform_trace/src/waveform_trace_tool.py
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tools/waveform_trace/src/waveform_trace_tool.py
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#
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# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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# 提取自: verilog_tools_class.py
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# 用途: 波形追踪工具 - 完整封装
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#
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import os
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import re
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from typing import Annotated
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from debug_graph_analyzer import DebugGraph
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from vcd_waveform_analyzer import parse_mismatch, get_tabular
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def check_functionality(vvp_output: str) -> bool:
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"""检查仿真输出是否有mismatch"""
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lines = vvp_output.splitlines()
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mismatches = None
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for line in lines:
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if re.match("^Mismatches:", line):
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mismatches = int(line.split()[1])
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break
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elif re.match("^Hint: Total mismatched samples is ", line):
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mismatches = int(line.split()[5])
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break
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if mismatches is None:
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return True # 没找到mismatch信息，认为通过
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return mismatches == 0
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def get_input_ports(verilog_code: str) -> list:
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"""从Verilog代码中提取输入端口"""
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input_ports = []
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lines = verilog_code.splitlines()
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for line in lines:
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# 匹配 input 声明
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match = re.search(r'input\s+(?:wire|reg)?\s*(?:\[[^\]]+\])?\s*(\w+)', line)
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if match:
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input_ports.append(match.group(1))
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return input_ports
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class WaveformTracer:
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"""波形追踪工具类"""
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def __init__(self, verilog_file_path: str, vcd_file_path: str):
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self.verilog_file_path = verilog_file_path
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self.vcd_file_path = vcd_file_path
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self.graph_tracer = None
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self.cur_verilog_content = ""
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def _load_verilog(self) -> str:
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"""加载Verilog文件内容"""
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with open(self.verilog_file_path, 'r', encoding='utf-8') as f:
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return f.read()
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def waveform_trace_tool(
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self,
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function_check_output: Annotated[str, "仿真工具的输出字符串"],
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trace_level: Annotated[int, "信号回溯层数，应大于1"]
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) -> str:
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"""
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波形追踪工具 - 核心函数
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参数:
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- function_check_output: 仿真工具的输出（包含mismatch信息）
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- trace_level: BFS回溯层数
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返回:
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- 包含信号追踪链、波形表、代码片段的字符串
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"""
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# 1. 检查文件是否存在
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if not os.path.exists(self.vcd_file_path):
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return "[Error] wave.vcd is not found! Please run simulation first!"
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if not os.path.exists(self.verilog_file_path):
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return "[Error] Verilog file is not found!"
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# 2. 加载Verilog代码
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verilog_content = self._load_verilog()
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# 3. 构建AST调试图（如果代码有变化则重建）
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if self.cur_verilog_content != verilog_content:
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print("Creating new AST tree graph...")
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self.graph_tracer = DebugGraph([self.verilog_file_path])
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self.cur_verilog_content = verilog_content
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# 4. 检查是否有mismatch
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print("Get mismatched signal...")
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if check_functionality(function_check_output):
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print("No mismatched signals")
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return "[Waveform Tracer]: No mismatched signals!"
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# 5. 解析mismatch信息
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mismatch_columns, offset = parse_mismatch(test_output=function_check_output)
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# 6. BFS回溯，找到控制信号
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print("Trace graph signal...")
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traced_signals_map, signal_level_tracer = self.graph_tracer.get_k_control_signals(
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target_signals=mismatch_columns,
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k=trace_level,
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signal_only=True
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)
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# 7. 格式化信号追踪链
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traced_signal_str = "[Signal Traces] Backtrace control signal relations.\n"
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for bt in range(len(signal_level_tracer) - 1, -1, -1):
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if bt == len(signal_level_tracer) - 1:
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for signal_rel in signal_level_tracer[bt]:
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traced_signal_str += signal_rel + "\n"
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header_space = "-" * (len(signal_level_tracer) - 1 - bt)
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for signal_rel in signal_level_tracer[bt]:
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traced_signal_str += header_space + signal_rel
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if bt == 0:
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traced_signal_str += " (*last output port level)"
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traced_signal_str += "\n"
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traced_signal_str += "\n"
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# 8. 收集所有需要追踪的信号
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all_traced_signals = [str(k) for k in traced_signals_map.keys()]
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# 9. 添加输入端口
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input_ports = get_input_ports(verilog_content)
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for inp in input_ports:
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mismatch_columns.append(inp)
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if inp not in all_traced_signals:
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all_traced_signals.append(inp)
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# 10. 获取波形表
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print("Get table waveform...")
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waveform_table_str = get_tabular(
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method='dataframe',
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vcd_path=self.vcd_file_path,
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mismatch_columns=all_traced_signals,
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offset=offset,
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ori_mismatch_columns=mismatch_columns
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)
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# 11. 格式化波形信息
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waveform_table_str = (
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"[Signal Waveform]: <signal>_tb is the given testbench signal and can not be changed! "
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"<signal>_ref is the golden, and <signal>_dut is the generated verilog file waveform. "
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"Check the mismatched signal waveform and its traced signals. "
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"The clock cycle (clk) is 10ns and toggles every 5ns.\n"
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"'-' means unknown during simulation. "
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"If the '-' is the reason of mismatched signal, please check the reset and assignment block.\n"
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f"[Testbench Input Port Signal to Module]: {', '.join(input_ports)}\n"
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f"[Traced Signals]: {', '.join(all_traced_signals)}\n"
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f"[Table Waveform in hexadecimal format]\n{waveform_table_str}"
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)
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# 12. 读取Verilog代码
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with open(self.verilog_file_path, 'r', encoding='utf-8') as f:
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verilog_lines = f.readlines()
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logic_str = "[Verilog of DUT]:\n```verilog\n" + ''.join(verilog_lines) + "\n```\n"
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# 13. 生成提示信息
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HINT = (
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f"\n\n[Note] You can not change the [testbench input signal]: ({', '.join(input_ports)})! "
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"Modify the module implementation considering the input signals.\n"
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"[Hint] Firstly, identify the time of mismatched signals, and only focus on the mismatched signals in the waveform firstly. "
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"Then, explain the related signals and their transitions in the waveform table. "
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"Don't correct signals without mismatch in the table waveforms. "
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"If the information is not enough for correct the functional error, "
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f"try to trace more relevant signals using trace_level > {trace_level} for waveform_trace_tool."
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)
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# 14. 如果mismatch发生在开始时，添加初始化提示
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if offset <= 5:
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HINT += (
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"\n\n[Debug report]: The mismatch happened at the beginning. "
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"Check and set the correct initial value for mismatched signal.\n"
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"### Example of initialize the signal to 0 ###\n\n"
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"logic [3:0] a;\ninitial\n a=4'b0000;\n\n"
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"### End example ###"
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)
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return logic_str + waveform_table_str + HINT
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# ============ 使用示例 ============
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if __name__ == '__main__':
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# 示例用法
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tracer = WaveformTracer(
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verilog_file_path="path/to/your/module.v",
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vcd_file_path="path/to/your/wave.vcd"
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)
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# 假设这是仿真输出
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sim_output = """
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Mismatches: 3
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Time 100ns: count expected=0001, got=0000
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"""
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result = tracer.waveform_trace_tool(
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function_check_output=sim_output,
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trace_level=2
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)
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print(result)
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