feat:接入iverilog工具

- 将iverilog可以随着插件的下载而下载
- 用户输入自然语言就可以控制生成对应的VCD文件

tools/iverilog/lib/include/constants.vams

@@ -0,0 +1,43 @@
+// Mathematical and physical constants
+
+`ifdef CONSTANTS_VAMS
+`else
+`define CONSTANTS_VAMS 1
+
+// M_ is a mathematical constant
+`define M_E        2.7182818284590452354
+`define M_LOG2E    1.4426950408889634074
+`define M_LOG10E   0.43429448190325182765
+`define M_LN2      0.69314718055994530942
+`define M_LN10     2.30258509299404568402
+`define M_PI       3.14159265358979323846
+`define M_TWO_PI   6.28318530717958647693
+`define M_PI_2     1.57079632679489661923
+`define M_PI_4     0.78539816339744830962
+`define M_1_PI     0.31830988618379067154
+`define M_2_PI     0.63661977236758134308
+`define M_2_SQRTPI 1.12837916709551257390
+`define M_SQRT2    1.41421356237309504880
+`define M_SQRT1_2  0.70710678118654752440
+
+/*
+ * Do we need these? For now they are not available.
+ *
+// The following constants have been taken from http://physics.nist.gov
+// P_ is a physical constant
+// charge of electron in coulombs
+`define P_Q        1.602176462e-19
+// speed of light in vacuum in meters/sec
+`define P_C        2.99792458e8
+// Boltzmann's constant in joules/kelvin
+`define P_K        1.3806503e-23
+// Planck's constant in joules*sec
+`define P_H        6.62606876e-34
+// permittivity of vacuum in farads/meter
+`define P_EPS0     8.854187817e-12
+// permeability of vacuum in henrys/meter
+`define P_U0       (4.0e-7 * `M_PI)
+// zero celsius in kelvin
+`define P_CELSIUS0 273.15
+*/
+`endif

tools/iverilog/lib/include/disciplines.vams

@@ -0,0 +1,72 @@
+
+// Standard definitions for Verilog-AMS
+`ifdef DISCIPLINES_VAMS
+`else
+`define DISCIPLINES_VAMS 1
+
+discipline \logic ;
+  domain discrete;
+enddiscipline
+
+discipline ddiscrete;
+  domain discrete;
+enddiscipline
+
+nature Current;
+  units      = "A";
+  access     = I;
+  idt_nature = Charge;
+`ifdef CURRENT_ABSTOL
+  abstol     = `CURRENT_ABSTOL
+`else
+  abstol     = 1e-12;
+`endif
+endnature
+
+nature Charge;
+  units      = "coul";
+  access     = Q;
+  ddt_nature = Current;
+`ifdef CHARGE_ABSTOL
+  abstol     = `CHARGE_ABSTOL;
+`else
+  abstol     = 1e-14;
+`endif
+endnature
+
+nature Voltage;
+  units      = "V";
+  access     = V;
+  idt_nature = Flux;
+`ifdef VOLTAGE_ABSTOL
+  abstol     = `VOLTAGE_ABSTOL;
+`else
+  abstol     = 1e-6;
+`endif
+endnature
+
+nature Flux;
+  units      = "Wb";
+  access     = Phi;
+  ddt_nature = Voltage;
+`ifdef FLUX_ABSTOL
+  abstol     = `flux_ABSTOL;
+`else
+  abstol     = 1e-9;
+`endif
+endnature
+
+discipline electrical;
+  potential Voltage;
+  flow Current;
+enddiscipline
+
+discipline voltage;
+  potential Voltage;
+enddiscipline
+
+discipline current;
+  flow Current;
+enddiscipline
+
+`endif // !`ifdef DISCIPLINES_VAMS

tools/iverilog/lib/ivl/blif-s.conf

@@ -0,0 +1,6 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:cprop
+functor:nodangle
+flag:DLL=blif.tgt

tools/iverilog/lib/ivl/blif.conf

@@ -0,0 +1,6 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:cprop
+functor:nodangle
+flag:DLL=blif.tgt

tools/iverilog/lib/ivl/null-s.conf

@@ -0,0 +1,4 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+flag:DLL=null.tgt

tools/iverilog/lib/ivl/null.conf

@@ -0,0 +1 @@
+flag:DLL=null.tgt

tools/iverilog/lib/ivl/pcb-s.conf

@@ -0,0 +1,6 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:cprop
+functor:nodangle
+flag:DLL=pcb.tgt

tools/iverilog/lib/ivl/pcb.conf

@@ -0,0 +1,3 @@
+functor:cprop
+functor:nodangle
+flag:DLL=pcb.tgt

tools/iverilog/lib/ivl/sizer-s.conf

@@ -0,0 +1,6 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:cprop
+functor:nodangle
+flag:DLL=sizer.tgt

tools/iverilog/lib/ivl/sizer.conf

@@ -0,0 +1,6 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:cprop
+functor:nodangle
+flag:DLL=sizer.tgt

tools/iverilog/lib/ivl/stub-s.conf

@@ -0,0 +1,6 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:cprop
+functor:nodangle
+flag:DLL=stub.tgt

tools/iverilog/lib/ivl/stub.conf

@@ -0,0 +1,3 @@
+functor:cprop
+functor:nodangle
+flag:DLL=stub.tgt

tools/iverilog/lib/ivl/vhdl-s.conf

@@ -0,0 +1,7 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:cprop
+functor:nodangle
+-t:dll
+flag:DLL=vhdl.tgt

tools/iverilog/lib/ivl/vhdl.conf

@@ -0,0 +1,4 @@
+functor:cprop
+functor:nodangle
+flag:DLL=vhdl.tgt
+flag:DISABLE_CONCATZ_GENERATION=true

tools/iverilog/lib/ivl/vlog95-s.conf

@@ -0,0 +1,7 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:nodangle
+functor:exposenodes
+flag:DLL=vlog95.tgt
+flag:DISABLE_CONCATZ_GENERATION=true

tools/iverilog/lib/ivl/vlog95.conf

@@ -0,0 +1,2 @@
+flag:DLL=vlog95.tgt
+flag:DISABLE_CONCATZ_GENERATION=true

tools/iverilog/lib/ivl/vvp-s.conf

@@ -0,0 +1,7 @@
+functor:synth2
+functor:synth
+functor:syn-rules
+functor:cprop
+functor:nodangle
+flag:DLL=vvp.tgt
+flag:VVP_EXECUTABLE=/c/Source/iverilog-install/bin/vvp

tools/iverilog/lib/ivl/vvp.conf

@@ -0,0 +1,4 @@
+functor:cprop
+functor:nodangle
+flag:DLL=vvp.tgt
+flag:VVP_EXECUTABLE=/c/Source/iverilog-install/bin/vvp